1. Field of the Invention
The present invention relates to a simulation method and simulation apparatus which are used for the execution of device design and circuit simulation for SOI-MOSFETs.
2. Description of the Related Art
Recently, with increases in portable devices, demands for high-speed, low-power-consumption devices have increased. As a technique which meets such demands and achieves an increase in the speed of CMOS LSIs and a reduction in power consumption of them, a so-called SOI-MOSFET, which has a MOSFET formed on a silicon-on-insulator (SOI) substrate, has been used.
An SOI-MOSFET is obtained by forming a buried oxide film called a BOX [buried oxide] under a channel region of a bulk-MOSFET (general MOSFET) and forming a channel in a thin silicon layer on the buried oxide film.
In FIGS. 1(a) and (b) respectively show the cross-sectional arrangements of the above bulk-MOSFET and SOI-MOSFET. Referring to (a) and (b) in FIG. 1, reference number 11 denotes a semiconductor substrate (also called a bulk in the case of an SOI-MOSFET); 12, a buried oxide film (BOX); 13, a silicon layer (SOI layer); 14, a source region; 15, a drain region; 16, a channel region; 17, a gate oxide film (FOX: front oxide in the case of an SOI-MOSFET); and 18, a gate electrode.
The SOI-MOSFET is smaller in stray capacitance than the bulk-MOSFET because of the buried oxide film 12 provided under the channel region 16, and hence can reduce switching delay. This can also reduce leakage currents to the semiconductor substrate 11.
Such SOI-MOSFETs are classified into three types according to the thickness of the above silicon layer (SOI layer), namely the fully depleted type, partially depleted type, and non-fully depleted type. In a non-fully depleted SOI-MOSFET, the depletion layer in the SOI layer 13 does not reach the buried oxide film 12 under normal voltage conditions, and the MOSFET exhibits characteristics similar to those of a bulk-MOSFET. In a partially depleted SOI-MOSFET, only the depletion layer at the drain end of the SOI layer 13 reaches the buried oxide film 12 under normal voltage conditions. In a fully depleted SOI-MOSFET, the entire SOI layer 13 is depleted under normal voltage conditions, and the MOSFET exhibits characteristics most different from those of a bulk-MOSFET.
The above fully depleted SOI-MOSFET has the following merits.
(1) Since the silicon layer in which a channel is formed is thin, leakage currents at a deep portion below the gate electrode can be suppressed.
(2) When the SOI layer is in a depleted state, since the gate capacitance is small, the sub-threshold swing is small.
(3) Since the substrate-voltage dependence of the threshold voltage is small, the saturated current is large.
(4) Since an insulator is provided between the source and drain regions (diffusion layer) and the substrate, the junction capacitance is small.
As described above, a fully depleted SOI-MOSFET is a high-speed, low-power-consumption device and is expected to have a wide range of applications. In order to allow circuit design exploiting the merits of such a fully depleted SOI-MOSFET, several circuit simulation models have been developed. Known main models include, for example, the BSIM (Berkely short-channel IGFET model-SOI) described in non-patent document 1 and the University of Florida SOI (UFSIM) described in non-patent document 2. These models are provided with important characteristics unique to SOI-MOSFETs, e.g., a parasitic bipolar effect and a generation-recombination current. In addition, they are also made in consideration of smooth transition from a partially depleted state to a fully depleted state.
These models, however, have been developed as extensions of bulk-MOSFET models, and hence have not been able to solve the problem of non-convergence in circuit simulations. This problem associated with convergence seems to originate from a violation of the law of conservation of charge.
The Hiroshima University STARC IGFET Model (HiSIM) uses a method of calculating the surface charge by deriving the surface potential using a single expression (diffusion-drift expression) in the operation from weak inversion to strong inversion of a MOSFET, thereby obtaining a current (see, for example, non-patent document 3). The voltage-current characteristic of a MOSFET obtained in this technique allows to reproduce actual measurement values properly with relatively simple calculations. However, since HiSIM is also a bulk-MOSFET model, the application of this technique to an SOI-MOSFET will lead to deterioration in stability and accuracy.
As indicated by the potential chart of FIG. 2, in the SOI-MOSFET, potentials φs0.bulk, φb0.SOI, and φs0.SOI are respectively generated at an interface BB between the bulk and the BOX, an interface BS between the BOX and the SOI layer, and an interface SF between the SOI layer and the FOX. Referring to FIG. 2, reference symbol Qbulk denotes charge in the bulk per unit area; QSOI, charge in the SOI layer per unit area; φSOI, a potential change at the SOI layer; Vgs, a gate-source voltage; and Vfb, a flat-band voltage.
Potentials φs0.bulk, φb0.SOI, and φs0.SOI described above become factors that cause variation in surface potentials at the source and drain region ends which are used by a bulk-MOSFET model of HiSIM, leading to deterioration in stability and accuracy. Demands have arisen for a simulation method and simulation apparatus which can extend HiSIM into a model capable of covering an SOI-MOSFET structure and perform stable, accurate simulation.